SI5040-D-GM【PDF 100/108 页】IC TXRX XFP 10GBPS 32LGA

您好，
买卖IC网欢迎您。
请登录
免费注册

96页 97页 98页 99页 [100页]101页 102页 103页 104页

Si5040

14. Pin Descriptions: Si5040

32

31

30

29

28

27

26

25

GND

1

24

SCK

RX_LOL

RX_LOS

VDDIO

GND

RXDIN–

RXDIN+

GND

2

3

4

5

6

7

8

GND

PAD

GND

PAD

GND

PAD

GND

PAD

23

22

21

20

19

18

17

GND

TD+

TD–

GND

RD+

RD–

GND

9

10

11

12

13

14

15

16

Figure 24. Si5040 Pin Configuration (Transparent Top View)

Table 13. Si5040 Pin Descriptions

Pin

16

Name

INTERRUPT

Type*

DO

Level

LVTTL

Interrupt (Active Low).

Description

or Open Drain

The interrupt output pin is provided to indicate potential fault

conditions or changes in status. Interrupt sources are mask-

able by setting the Interrupt Mask register, and interrupt status

is available from the Interrupt Status register. The interrupt

function can be disabled in the Interrupt Enable bit. The inter-

rupt pin can be configured via the Interrupt Output register as

either an open drain output (default) or LVTTL output.

19,18

RD+

RD–

AO

Differential CML Receiver Data Output.

High-speed XFI-compliant receiver data output recovered

from the RXDIN input.

13,14

REFCLK+

AI

PECL

Reference Clock Input.

REFCLK–

A reference clock at this input is applied to the transmit CMU

and to the receiver and transmitter CDRs. The use of a refer-

ence clock is optional.

If the jitter performance of the external reference clock is

acceptable, the Si5040 can be operated in CMU mode. In this

mode, the CMU derives the line-rate clock by multiplying the

clock frequency applied to the REFCLK inputs. If the REFCLK

input is synchronous, the CMU multiplies the frequency by 64.

The resulting line-rate is frequency-locked to the serial data. A

FIFO in the data path accommodates any jitter differences

between the serial data and the CMU line-rate clock.

7, 6

RXDIN+

RXDIN–

AI

Differential CML Receiver Data Input.

Data signal RD is recovered from the high-speed differential

signal present on these pins.

Data over the 9.8304 Gbps to 11.3 Gbps range is recovered.

*Note: TYPE: P = Power; AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital

Input/Output.

100

Rev. 1.3

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

我的联系方式

*

*

*

相关PDF资料

SI5402DC-T1-GE3 MOSFET N-CH D-S 30V 1206-8

SI5403DC-T1-GE3 MOSFET P-CH 30V 6A 1206-8

SI5432DC-T1-GE3 MOSFET N-CH 20V 6A 1206-8

SI5440DC-T1-GE3 MOSFET N-CH D-S 30V 1206-8

SI5441DC-T1-GE3 MOSFET P-CH D-S 20V 1206-8

SI5443DC-T1-GE3 MOSFET P-CH D-S 20V 1206-8

SI5468DC-T1-GE3 MOSFET N-CH D-S 30V 1206-8

SI5475BDC-T1-GE3 MOSFET P-CH 12V 6A 1206-8

相关代理商/技术参数

SI5040-D-GMR 制造商:Silicon Laboratories Inc 功能描述:XFP Transceiver 1TX 1RX 10Gbps 32-Pin LGA T/R 制造商:Silicon Laboratories Inc 功能描述:XFP TRANSCEIVER, PB FREE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC TXRX XFP 10GBPS 32LGA

SI5040-D-ZM2 制造商:Silicon Laboratories Inc 功能描述:XFP TRANSCEIVER, PB FREE - Rail/Tube

SI5040-D-ZM6 制造商:Silicon Laboratories Inc 功能描述:XFP TRANSCEIVER - Rail/Tube

SI5040-D-ZM7 制造商:Silicon Laboratories Inc 功能描述:XFP TRANSCEIVER, PB FREE - Rail/Tube

SI5040-EVB 功能描述:BOARD EVAL SI5040 RoHS:否类别:编程器，开发系统 >> 评估演示板和套件系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器嵌入式:否已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池次要属性:状态 LED 已供物品:板

SI5041-B-GM 制造商:Silicon Laboratories Inc 功能描述:10G DUAL CDR (REV B FOR PROTOTYPE ONLY, REV C FOR P - Rail/Tube

SI5041-B-GMR 制造商:Silicon Laboratories Inc 功能描述:10G DUAL CDR (REV B FOR PROTOTYPE ONLY, REV C FOR P - Tape and Reel

SI5041-C-GM 制造商:Silicon Laboratories Inc 功能描述:10G DUAL CDR, LEAD FREE - Rail/Tube